PCIバス用テストベンチ関連ソースファイル
pci_master_access_2target.vht
■リンク元 PCIバス向けテストベンチ用サブプログラム
●テストベンチ本体のソース pci_master_access_2target.vht
-------------------------------------------------------------------------------------
-- File Name : pci_master_access_2target.vht
-- Function : pci_master_access test_bench for 2 targets
-- Author : F.O. (ProXi)
-- Date : 2018/11/15
-- Company : ProXi
-- 【備考】 : 詳細は https://www.proxi.co.jp/technolo/pci_bus_test_bench.htm 参照
-- : 本ソースは ASIAN記法 (Attributed SIgnAl Naming) で記述している。
-- : 詳細は https://www.proxi.co.jp/technolo/asian.htm 参照
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.ALL;
use work.pci_master_access_pac.all;
entity pci_master_access_target IS
end pci_master_access_target;
architecture pci_model_sim_arch OF pci_master_access_target IS
-- constants
constant clk_period : time := 30.3 ns; -- 33MHz
constant IDSEL0 : integer := 0; -- IDSEL_no of target0
constant IDSEL1 : integer := 1; -- IDSEL_no of target1
constant PAR_OK : std_logic := '0'; -- set parity ok
constant PAR_NG : std_logic := '1'; -- set parity ng
constant BEn_1110 : std_logic_vector := "1110"; -- byte enable (active low)
constant BEn_1101 : std_logic_vector := "1101"; -- byte enable (active low)
constant BEn_1011 : std_logic_vector := "1011"; -- byte enable (active low)
constant BEn_0111 : std_logic_vector := "0111"; -- byte enable (active low)
constant BEn_1100 : std_logic_vector := "1100"; -- byte enable (active low)
constant BEn_1010 : std_logic_vector := "1010"; -- byte enable (active low)
constant BEn_0110 : std_logic_vector := "0110"; -- byte enable (active low)
constant BEn_1001 : std_logic_vector := "1001"; -- byte enable (active low)
constant BEn_0101 : std_logic_vector := "0101"; -- byte enable (active low)
constant BEn_0011 : std_logic_vector := "0011"; -- byte enable (active low)
constant BEn_1000 : std_logic_vector := "1000"; -- byte enable (active low)
constant BEn_0100 : std_logic_vector := "0100"; -- byte enable (active low)
constant BEn_0010 : std_logic_vector := "0010"; -- byte enable (active low)
constant BEn_0001 : std_logic_vector := "0001"; -- byte enable (active low)
constant BEn_0000 : std_logic_vector := "0000"; -- byte enable (active low)
constant CONT_DATA : std_logic := '0'; -- not last_data when burst write
constant LAST_DATA : std_logic := '1'; -- last_data when burst write
constant DATA_No_1 : integer := 1; -- burst read data_no = 1 data
constant DATA_No_2 : integer := 2; -- burst read data_no = 2 data
constant DATA_No_3 : integer := 3; -- burst read data_no = 3 data
constant DATA_No_4 : integer := 4; -- burst read data_no = 4 data
constant SET_RAM_ADR_WIDTH : integer := 10; -- sram address bit --Note1
-- signals
signal master_event_no : integer := 0;
signal sva_read_data0 : DATA_ARRAY := (x"0000_0000", x"0000_0000", x"0000_0000", x"0000_0000"); -- for test
signal sva_read_data1 : DATA_ARRAY := (x"0000_0000", x"0000_0000", x"0000_0000", x"0000_0000"); -- for test
signal xsva_set_data : SET_DATA_ARRAY;
-- PCIバス信号ピン(ターゲット8で使用する信号) --
signal clk : std_logic; -- pciバスクロック
signal rst_n : std_logic := '0'; -- 非同期リセット
signal ad : std_logic_vector(31 downto 0); -- アドレス/データバス
signal c_be_n : std_logic_vector(3 downto 0); -- pciバスコマンド/バイトイネーブル
signal frame_n : std_logic; -- フレーム
signal irdy_n : std_logic; -- イニシエータレディ
signal devsel_n : std_logic; -- デバイスセレクション
signal trdy_n : std_logic; -- ターゲットレディ
signal v_idsel : std_logic_vector(31 downto 0); -- コンフィグレーションデバイスセレクト信号線
signal inta_n : std_logic; -- 割り込み出力 inta#
signal stop_n : std_logic; -- 転送ストップ要求
signal par : std_logic; -- パリティビット
signal perr_n : std_logic; -- パリティエラー
-- pciバス信号ピン(ターゲット8で未使用な信号) --
signal serr_n : std_logic; -- システムエラー
signal req_n : std_logic; -- バス使用要求信号
signal gnt_n : std_logic; -- バス使用許諾信号
signal intb_n : std_logic; -- 割り込み出力 intb#
signal intc_n : std_logic; -- 割り込み出力 intc#
signal intd_n : std_logic; -- 割り込み出力 intd#
signal lock_n : std_logic; -- 排他アクセス制御
signal sbo_n : std_logic; -- スヌープバックオフ
signal sdone_n : std_logic; -- スヌープ完了
-- SRAM0 信号ピン
signal mem_adrs0 : std_logic_vector(23 downto 2) := (others => 'Z'); -- メモリアドレスバス(16mバイト)
signal mem_data0 : std_logic_vector(31 downto 0) := (others => 'Z'); -- メモリデータバス
signal mem_cen0 : std_logic := '1'; -- sram0〜3 /ce
signal mem_oen0 : std_logic := '1'; -- sram0〜3 /oe
signal mem_we0n0 : std_logic := '1'; -- sram0 /we
signal mem_we1n0 : std_logic := '1'; -- sram1 /we
signal mem_we2n0 : std_logic := '1'; -- sram2 /we
signal mem_we3n0 : std_logic := '1'; -- sram3 /we
signal av_di : std_logic_vector(7 downto 0) := (others => '0'); -- DI ポート
signal sv_do : std_logic_vector(7 downto 0) := (others => '0'); -- DO ポート
-- SRAM1 信号ピン
signal mem_adrs1 : std_logic_vector(23 downto 2) := (others => 'Z'); -- メモリアドレスバス(16mバイト)
signal mem_data1 : std_logic_vector(31 downto 0) := (others => 'Z'); -- メモリデータバス
signal mem_cen1 : std_logic := '1'; -- sram0〜3 /ce
signal mem_oen1 : std_logic := '1'; -- sram0〜3 /oe
signal mem_we0n1 : std_logic := '1'; -- sram0 /we
signal mem_we1n1 : std_logic := '1'; -- sram1 /we
signal mem_we2n1 : std_logic := '1'; -- sram2 /we
signal mem_we3n1 : std_logic := '1'; -- sram3 /we
-- for test
--signal tp0 : std_logic;
--signal tp1 : std_logic;
--signal tp2 : std_logic;
--signal tp3 : std_logic;
--signal tp4 : std_logic;
--signal tp5 : std_logic;
--signal tp6 : std_logic;
--signal tp7 : std_logic;
--signal tp_v0 : std_logic_vector(31 downto 0);
--signal tp_v1 : std_logic_vector(3 downto 0);
--signal tp_v2 : std_logic_vector(31 downto 0)
--signal tp_v3 : std_logic_vector(3 downto 0);
--signal cv_cur_state0 : std_logic_vector(2 downto 0);
--signal cv_cur_state1 : std_logic_vector(2 downto 0);
-- 外部割り込み入力ピン
signal int_in3 : std_logic := '1'; -- 割り込み入力3
signal int_in2 : std_logic := '1'; -- 割り込み入力2
signal int_in1 : std_logic := '1'; -- 割り込み入力1
signal int_in0 : std_logic := '1'; -- 割り込み入力0
component TGT8
port (
-- PCIバス信号ピン(ターゲット8で使用する信号) --
PCICLK : in std_logic; -- PCIバスクロック
RST_n : in std_logic; -- 非同期リセット
PCIAD : inout std_logic_vector(31 downto 0); -- アドレス/データバス
C_BE_n : in std_logic_vector(3 downto 0); -- PCIバスコマンド/バイトイネーブル
FRAME_n : in std_logic; -- フレーム
IRDY_n : in std_logic; -- イニシエータレディ
DEVSEL_n : out std_logic; -- デバイスセレクション
TRDY_n : out std_logic; -- ターゲットレディ
IDSEL : in std_logic; -- コンフィグレーションデバイスセレクト
INTA_n : out std_logic; -- 割り込み出力 INTA#
STOP_n : out std_logic; -- 転送ストップ要求
PAR : inout std_logic; -- パリティビット
PERR_n : out std_logic; -- パリティエラー
-- PCIバス信号ピン(ターゲット8で未使用な信号) --
SERR_n : out std_logic; -- システムエラー
REQ_n : out std_logic; -- バス使用要求信号
GNT_n : in std_logic; -- バス使用許諾信号
INTB_n : out std_logic; -- 割り込み出力 INTB#
INTC_n : out std_logic; -- 割り込み出力 INTC#
INTD_n : out std_logic; -- 割り込み出力 INTD#
LOCK_n : in std_logic; -- 排他アクセス制御
SBO_n : inout std_logic; -- スヌープバックオフ
SDONE_n : inout std_logic; -- スヌープ完了
-- 外部割り込み入力ピン
INT_IN0 : in std_logic; -- 割り込み入力0
INT_IN1 : in std_logic; -- 割り込み入力1
INT_IN2 : in std_logic; -- 割り込み入力2
INT_IN3 : in std_logic; -- 割り込み入力3
-- ローカルバス信号ピン
MEM_ADRS : out std_logic_vector(23 downto 2); -- メモリアドレスバス(16Mバイト)
MEM_DATA : inout std_logic_vector(31 downto 0); -- メモリデータバス
MEM_CEn : out std_logic; -- SRAM0〜3 /CE
MEM_OEn : out std_logic; -- SRAM0〜3 /OE
MEM_WE0n : out std_logic; -- SRAM0 /WE
MEM_WE1n : out std_logic; -- SRAM1 /WE
MEM_WE2n : out std_logic; -- SRAM2 /WE
MEM_WE3n : out std_logic; -- SRAM3 /WE
av_di : in std_logic_vector(7 downto 0); -- DIポート
sv_do : out std_logic_vector(7 downto 0); -- DOポート
-- for test
tp0 : out std_logic;
tp1 : out std_logic;
tp2 : out std_logic;
tp3 : out std_logic;
tp4 : out std_logic;
tp5 : out std_logic;
tp6 : out std_logic;
tp7 : out std_logic;
tp_v0 : out std_logic_vector(31 downto 0);
tp_v1 : out std_logic_vector(3 downto 0);
tp_v2 : out std_logic_vector(31 downto 0);
tp_v3 : out std_logic_vector(3 downto 0);
cv_cur_state: out std_logic_vector(2 downto 0)
);
end component;
component sram_8_model
generic ( RAM_ADR_WIDTH : integer := 4; -- ram address width
SET_HIZ_VAL : std_logic := 'Z'; -- select one from 'Z','H','L'
t_OE : time := 20.0 ns -- time bitween output enable to output valid
);
port (
-- in
a_cs_l : in std_logic;
a_rd_l : in std_logic;
a_wr_l : in std_logic;
av_adr : in std_logic_vector(RAM_ADR_WIDTH-1 downto 0);
-- inout
av_data : inout std_logic_vector(7 downto 0)
);
end component;
begin
-- TARGET0
tg8_0 : TGT8
port map (
RST_n => rst_n,
PCICLK => clk,
C_BE_n => c_be_n,
DEVSEL_n => devsel_n,
FRAME_n => frame_n,
GNT_n => gnt_n,
IDSEL => v_idsel(IDSEL0), -- connect v_idsel(IDSEL0) line to IDSEL
PAR => par,
PCIAD => ad,
PERR_n => perr_n,
REQ_n => req_n,
SBO_n => sbo_n,
SDONE_n => sdone_n,
SERR_n => serr_n,
STOP_n => stop_n,
TRDY_n => trdy_n,
INT_IN0 => int_in0,
INT_IN1 => int_in1,
INT_IN2 => int_in2,
INT_IN3 => int_in3,
INTA_n => inta_n,
INTB_n => intb_n,
INTC_n => intc_n,
INTD_n => intd_n,
IRDY_n => irdy_n,
LOCK_n => lock_n,
MEM_ADRS => mem_adrs0,
MEM_CEn => mem_cen0,
MEM_DATA => mem_data0,
MEM_OEn => mem_oen0,
MEM_WE0n => mem_we0n0,
MEM_WE1n => mem_we1n0,
MEM_WE2n => mem_we2n0,
MEM_WE3n => mem_we3n0,
av_di => av_di,
sv_do => sv_do,
-- for test
tp0 => open,
tp1 => open,
tp2 => open,
tp3 => open,
tp4 => open,
tp5 => open,
tp6 => open,
tp7 => open,
tp_v0 => open,
tp_v1 => open,
tp_v2 => open,
tp_v3 => open,
--cv_cur_state => cv_cur_state0, -- for test
cv_cur_state => open
);
-- TARGET1
tg8_1 : TGT8
port map (
RST_n => rst_n,
PCICLK => clk,
C_BE_n => c_be_n,
DEVSEL_n => devsel_n,
FRAME_n => frame_n,
GNT_n => gnt_n,
IDSEL => v_idsel(IDSEL1), -- connect v_idsel(IDSEL1) line to IDSEL
PAR => par,
PCIAD => ad,
PERR_n => perr_n,
REQ_n => req_n,
SBO_n => sbo_n,
SDONE_n => sdone_n,
SERR_n => serr_n,
STOP_n => stop_n,
TRDY_n => trdy_n,
INT_IN0 => '1',
INT_IN1 => '1',
INT_IN2 => '1',
INT_IN3 => '1',
INTA_n => inta_n,
INTB_n => intb_n,
INTC_n => intc_n,
INTD_n => intd_n,
IRDY_n => irdy_n,
LOCK_n => lock_n,
MEM_ADRS => mem_adrs1,
MEM_CEn => mem_cen1,
MEM_DATA => mem_data1,
MEM_OEn => mem_oen1,
MEM_WE0n => mem_we0n1,
MEM_WE1n => mem_we1n1,
MEM_WE2n => mem_we2n1,
MEM_WE3n => mem_we3n1,
av_di => (others => '0'),
sv_do => open,
-- for test
tp0 => open,
tp1 => open,
tp2 => open,
tp3 => open,
tp4 => open,
tp5 => open,
tp6 => open,
tp7 => open,
tp_v0 => open,
tp_v1 => open,
tp_v2 => open,
tp_v3 => open,
--cv_cur_state => cv_cur_state1, -- for test
cv_cur_state => open
);
sram00 : sram_8_model
generic map (
RAM_ADR_WIDTH => SET_RAM_ADR_WIDTH, -- ram address width
SET_HIZ_VAL => 'Z', -- select one from 'Z','H','L'
t_OE => 20.0 ns -- time bitween output enable to output valid
)
port map (
-- in
a_cs_l => mem_cen0,
a_rd_l => mem_oen0,
a_wr_l => mem_we0n0,
av_adr => mem_adrs0( (SET_RAM_ADR_WIDTH-1 +2) downto 2),
-- inout
av_data => mem_data0(7 downto 0)
);
sram01 : sram_8_model
generic map (
RAM_ADR_WIDTH => SET_RAM_ADR_WIDTH, -- ram address width
SET_HIZ_VAL => 'Z', -- select one from 'Z','H','L'
t_OE => 20.0 ns -- time bitween output enable to output valid
)
port map (
-- in
a_cs_l => mem_cen0,
a_rd_l => mem_oen0,
a_wr_l => mem_we1n0,
av_adr => mem_adrs0( (SET_RAM_ADR_WIDTH-1 +2) downto 2),
-- inout
av_data => mem_data0(15 downto 8)
);
sram02: sram_8_model
generic map (
RAM_ADR_WIDTH => SET_RAM_ADR_WIDTH, -- ram address width
SET_HIZ_VAL => 'Z', -- select one from 'Z','H','L'
t_OE => 20.0 ns -- time bitween output enable to output valid
)
port map (
-- in
a_cs_l => mem_cen0,
a_rd_l => mem_oen0,
a_wr_l => mem_we2n0,
av_adr => mem_adrs0( (SET_RAM_ADR_WIDTH-1 +2) downto 2),
-- inout
av_data => mem_data0(23 downto 16)
);
sram03: sram_8_model
generic map (
RAM_ADR_WIDTH => SET_RAM_ADR_WIDTH, -- ram address width
SET_HIZ_VAL => 'Z', -- select one from 'Z','H','L'
t_OE => 20.0 ns -- time bitween output enable to output valid
)
port map (
-- in
a_cs_l => mem_cen0,
a_rd_l => mem_oen0,
a_wr_l => mem_we3n0,
av_adr => mem_adrs0( (SET_RAM_ADR_WIDTH-1 +2) downto 2),
-- inout
av_data => mem_data0(31 downto 24)
);
--------------------
sram10 : sram_8_model
generic map (
RAM_ADR_WIDTH => SET_RAM_ADR_WIDTH, -- ram address width
SET_HIZ_VAL => 'Z', -- select one from 'Z','H','L'
t_OE => 20.0 ns -- time bitween output enable to output valid
)
port map (
-- in
a_cs_l => mem_cen1,
a_rd_l => mem_oen1,
a_wr_l => mem_we0n1,
av_adr => mem_adrs1( (SET_RAM_ADR_WIDTH-1 +2) downto 2),
-- inout
av_data => mem_data1(7 downto 0)
);
sram11 : sram_8_model
generic map (
RAM_ADR_WIDTH => SET_RAM_ADR_WIDTH, -- ram address width
SET_HIZ_VAL => 'Z', -- select one from 'Z','H','L'
t_OE => 20.0 ns -- time bitween output enable to output valid
)
port map (
-- in
a_cs_l => mem_cen1,
a_rd_l => mem_oen1,
a_wr_l => mem_we1n1,
av_adr => mem_adrs1( (SET_RAM_ADR_WIDTH-1 +2) downto 2),
-- inout
av_data => mem_data1(15 downto 8)
);
sram12: sram_8_model
generic map (
RAM_ADR_WIDTH => SET_RAM_ADR_WIDTH, -- ram address width
SET_HIZ_VAL => 'Z', -- select one from 'Z','H','L'
t_OE => 20.0 ns -- time bitween output enable to output valid
)
port map (
-- in
a_cs_l => mem_cen1,
a_rd_l => mem_oen1,
a_wr_l => mem_we2n1,
av_adr => mem_adrs1( (SET_RAM_ADR_WIDTH-1 +2) downto 2),
-- inout
av_data => mem_data1(23 downto 16)
);
sram13: sram_8_model
generic map (
RAM_ADR_WIDTH => SET_RAM_ADR_WIDTH, -- ram address width
SET_HIZ_VAL => 'Z', -- select one from 'Z','H','L'
t_OE => 20.0 ns -- time bitween output enable to output valid
)
port map (
-- in
a_cs_l => mem_cen1,
a_rd_l => mem_oen1,
a_wr_l => mem_we3n1,
av_adr => mem_adrs1( (SET_RAM_ADR_WIDTH-1 +2) downto 2),
-- inout
av_data => mem_data1(31 downto 24)
);
-------------------
-- system reset
rst_n <= '0', '1' after 100 ns; -- deassert reset
-- sysclk process definitions
system_clk_process : process begin
clk <= '1';
wait for clk_period /2;
clk <= '0';
wait for clk_period /2;
end process;
-- DO/DI Loop Back
av_di <= not sv_do;
-- parity error message
error_display_process : process (perr_n) begin
assert (perr_n /= '0')
report "Parity Error Occur!"
severity ERROR;
--severity FAILURE;
end process;
----------------------------------------------------------------------
-- master access pci-bus
----------------------------------------------------------------------
master_access_process : process begin
-- Initialize
master_event_no <= 0;
pci_init (v_idsel, frame_n, ad, c_be_n, irdy_n, par, lock_n, req_n, perr_n, serr_n,
inta_n, intb_n, intc_n, intd_n);
wait until rst_n'event and rst_n='1';
int_in0 <= '1'; -- 割り込み入力3
int_in1 <= '1'; -- 割り込み入力2
int_in2 <= '1'; -- 割り込み入力1
int_in3 <= '1'; -- 割り込み入力0
wait until clk'event and clk='1';
wait until clk'event and clk='1';
--------------------------------
-- configure TGT0
--------------------------------
-- 0x0004 command set (memory access enable)
master_event_no <= master_event_no +1;
-- memory, i/o
pci_config_write (IDSEL0, x"0000_0004", PAR_OK, x"0000_0143", BEn_1100, PAR_OK,
clk, trdy_n, devsel_n, v_idsel, frame_n, ad, c_be_n, irdy_n, par);
---------------
-- 0x0004 command/status read
pci_config_read (IDSEL0, x"0000_0004", PAR_OK, BEn_1100,
clk, trdy_n, devsel_n, v_idsel, frame_n, ad, c_be_n, irdy_n, par, perr_n, sva_read_data0(0));
---------------
-- 0x0010 set base address 0 (for memory)
pci_config_write (IDSEL0, x"0000_0010", PAR_OK, x"ffff_ffff", BEn_0000, PAR_OK,
clk, trdy_n, devsel_n, v_idsel, frame_n, ad, c_be_n, irdy_n, par);
---------------
-- 0x0010 read base address 0
pci_config_read (IDSEL0, x"0000_0010", PAR_OK, BEn_0000,
clk, trdy_n, devsel_n, v_idsel, frame_n, ad, c_be_n, irdy_n, par, perr_n, sva_read_data0(0));
---------------
-- 0x0010 set base address 0 (for memory)
pci_config_write (IDSEL0, x"0000_0010", PAR_OK, x"a000_0000", BEn_0000, PAR_OK, -- set memory address x"a000_0000"
clk, trdy_n, devsel_n, v_idsel, frame_n, ad, c_be_n, irdy_n, par);
---------------
-- 0x0010 read base address 0
pci_config_read (IDSEL0, x"0000_0010", PAR_OK, BEn_0000,
clk, trdy_n, devsel_n, v_idsel, frame_n, ad, c_be_n, irdy_n, par, perr_n, sva_read_data0(0));
---------------
-- 0x0014 set base address 1 (for i/o)
pci_config_write (IDSEL0, x"0000_0014", PAR_OK, x"ffff_ffff", BEn_0000, PAR_OK,
clk, trdy_n, devsel_n, v_idsel, frame_n, ad, c_be_n, irdy_n, par);
---------------
-- 0x0014 read base address 1
pci_config_read (IDSEL0, x"0000_0014", PAR_OK, BEn_0000,
clk, trdy_n, devsel_n, v_idsel, frame_n, ad, c_be_n, irdy_n, par, perr_n, sva_read_data0(0));
---------------
-- 0x0014 set base address 1 (for i/o)
pci_config_write (IDSEL0, x"0000_0014", PAR_OK, x"0000_8001", BEn_0000, PAR_OK, -- set i/o address x"8000"
clk, trdy_n, devsel_n, v_idsel, frame_n, ad, c_be_n, irdy_n, par);
---------------
-- 0x0014 read base address 1
pci_config_read (IDSEL0, x"0000_0014", PAR_OK, BEn_0000,
clk, trdy_n, devsel_n, v_idsel, frame_n, ad, c_be_n, irdy_n, par, perr_n, sva_read_data0(0));
---------------
-- 0x003C int set
pci_config_write (IDSEL0, x"0000_003c", PAR_OK, x"0000_0101", BEn_0000, PAR_OK,
clk, trdy_n, devsel_n, v_idsel, frame_n, ad, c_be_n, irdy_n, par);
----------------------------------
-- int unmask set
-- 0x8002 i/o write (d7-0 bits)
pci_io_write (x"0000_8002", PAR_OK, x"000f_0000", BEn_1011, PAR_OK,
clk, trdy_n, devsel_n, frame_n, ad, c_be_n, irdy_n, par);
wait until clk'event and clk='1';
wait until clk'event and clk='1';
wait until clk'event and clk='1';
wait until clk'event and clk='1';
--------------------------------
-- configure TGT1
--------------------------------
---------------
-- 0x0004 command set (memory access enable)
master_event_no <= master_event_no +1;
-- memory, i/o
pci_config_write (IDSEL1, x"0000_0004", PAR_OK, x"0000_0142", BEn_1100, PAR_OK,
clk, trdy_n, devsel_n, v_idsel, frame_n, ad, c_be_n, irdy_n, par);
---------------
-- 0x0004 command/status read
pci_config_read (IDSEL1, x"0000_0004", PAR_OK, BEn_1100,
clk, trdy_n, devsel_n, v_idsel, frame_n, ad, c_be_n, irdy_n, par, perr_n, sva_read_data1(0));
---------------
-- 0x0010 set base address 0 (for memory)
pci_config_write (IDSEL1, x"0000_0010", PAR_OK, x"ffff_ffff", BEn_0000, PAR_OK,
clk, trdy_n, devsel_n, v_idsel, frame_n, ad, c_be_n, irdy_n, par);
---------------
-- 0x0010 read base address 0
pci_config_read (IDSEL1, x"0000_0010", PAR_OK, BEn_0000,
clk, trdy_n, devsel_n, v_idsel, frame_n, ad, c_be_n, irdy_n, par, perr_n, sva_read_data1(0));
---------------
-- 0x0010 set base address 0 (for memory)
pci_config_write (IDSEL1, x"0000_0010", PAR_OK, x"b000_0000", BEn_0000, PAR_OK, -- set memory address x"b000_0000"
clk, trdy_n, devsel_n, v_idsel, frame_n, ad, c_be_n, irdy_n, par);
---------------
-- 0x0010 read base address 0
pci_config_read (IDSEL1, x"0000_0010", PAR_OK, BEn_0000,
clk, trdy_n, devsel_n, v_idsel, frame_n, ad, c_be_n, irdy_n, par, perr_n, sva_read_data1(0));
wait until clk'event and clk='1';
wait until clk'event and clk='1';
wait until clk'event and clk='1';
wait until clk'event and clk='1';
----------------------------------
-- TGT0 memory access
----------------------------------
----------------------------------
-- 0xa000_000x memory write (32 bits)
master_event_no <= master_event_no +1;
pci_memory_write (x"a000_0000", PAR_OK, x"0000_1111", BEn_0000, PAR_OK,
clk, trdy_n, devsel_n, frame_n, ad, c_be_n, irdy_n, par);
pci_memory_write (x"a000_0004", PAR_OK, x"2222_3333", BEn_0000, PAR_NG, -- set data parity NG
clk, trdy_n, devsel_n, frame_n, ad, c_be_n, irdy_n, par);
----------------------------------
-- 0xa000_000x memory read (32 bits)
pci_memory_read (x"a000_0000", PAR_OK, BEn_0000,
clk, trdy_n, devsel_n, frame_n, ad, c_be_n, irdy_n, par, perr_n, sva_read_data0(0));
pci_memory_read (x"a000_0004", PAR_NG, BEn_0000, -- set address parity NG
clk, trdy_n, devsel_n, frame_n, ad, c_be_n, irdy_n, par, perr_n, sva_read_data0(0));
----------------------------------
-- 0xa000_00xx memory burst write
xsva_set_data <= ( (x"8888_9999", BEn_0000, PAR_OK, CONT_DATA),
(x"aaaa_bbbb", BEn_0000, PAR_OK, CONT_DATA),
(x"cccc_dddd", BEn_0000, PAR_OK, CONT_DATA),
(x"eeee_ffff", BEn_0000, PAR_OK, LAST_DATA ) );
pci_memory_burst_write (x"a000_0008", PAR_OK, xsva_set_data,
clk, trdy_n, devsel_n, frame_n, ad, c_be_n, irdy_n, par);
----------------------------------
-- 0xa000_00xx memory burst read
pci_memory_burst_read (x"a000_0008", PAR_OK, DATA_No_4, (BEn_0000, BEn_0000, BEn_0000, BEn_0000),
clk, trdy_n, devsel_n, frame_n, ad, c_be_n, irdy_n, par, perr_n, sva_read_data0);
wait until clk'event and clk='1';
wait until clk'event and clk='1';
wait until clk'event and clk='1';
wait until clk'event and clk='1';
----------------------------------
-- TGT0 i/o access
----------------------------------
-- 0x8004 i/o write (d7-0 bits)
master_event_no <= master_event_no +1;
pci_io_write (x"0000_8004", PAR_OK, x"0000_005a", BEn_1110, PAR_OK,
clk, trdy_n, devsel_n, frame_n, ad, c_be_n, irdy_n, par);
-- 0x8004 i/o read (d7-0 bits)
pci_io_read (x"0000_8004", PAR_OK, BEn_1110,
clk, trdy_n, devsel_n, frame_n, ad, c_be_n, irdy_n, par, perr_n, sva_read_data0(0));
-- 0x8006 i/o read (d7-0 bits)
pci_io_read (x"0000_8006", PAR_OK, BEn_1110,
clk, trdy_n, devsel_n, frame_n, ad, c_be_n, irdy_n, par, perr_n, sva_read_data0(0));
wait until clk'event and clk='1';
wait until clk'event and clk='1';
wait until clk'event and clk='1';
wait until clk'event and clk='1';
--------------------------------
-- TGT0 interrupt
--------------------------------
master_event_no <= master_event_no +1;
wait until clk'event and clk='1';
int_in0 <= '0'; -- activate interrupt0
wait until clk'event and clk='1';
wait until clk'event and clk='1';
int_in0 <= '1'; -- negate interrupt0
wait until clk'event and clk='1';
----------------------------------
-- 0x8000 i/o read (d7-0 bits) int register read
pci_io_read (x"0000_8000", PAR_OK, BEn_1110,
clk, trdy_n, devsel_n, frame_n, ad, c_be_n, irdy_n, par, perr_n, sva_read_data0(0));
----------------------------------
-- 0x8000 i/o write (d7-0 bits)
pci_io_write (x"0000_8000", PAR_OK, x"0000_000f", BEn_1110, PAR_OK, -- int register clear
clk, trdy_n, devsel_n, frame_n, ad, c_be_n, irdy_n, par);
wait until clk'event and clk='1';
wait until clk'event and clk='1';
wait until clk'event and clk='1';
wait until clk'event and clk='1';
----------------------------------
-- TGT1 memory access
----------------------------------
----------------------------------
-- 0xb000_001x memory write (32 bits)
master_event_no <= master_event_no +1;
pci_memory_write (x"b000_0010", PAR_OK, x"ffff_eeee", BEn_0000, PAR_OK,
clk, trdy_n, devsel_n, frame_n, ad, c_be_n, irdy_n, par);
pci_memory_write (x"b000_0014", PAR_OK, x"dddd_cccc", BEn_0000, PAR_OK,
clk, trdy_n, devsel_n, frame_n, ad, c_be_n, irdy_n, par);
----------------------------------
-- 0xb000_001x memory read (32 bits)
pci_memory_read (x"b000_0010", PAR_OK, BEn_0000,
clk, trdy_n, devsel_n, frame_n, ad, c_be_n, irdy_n, par, perr_n, sva_read_data1(0));
pci_memory_read (x"b000_0014", PAR_OK, BEn_0000,
clk, trdy_n, devsel_n, frame_n, ad, c_be_n, irdy_n, par, perr_n, sva_read_data1(0));
----------------------------------
-- 0xb000_001x memory burst write
xsva_set_data <= ( (x"6666_5555", BEn_0000, PAR_OK, CONT_DATA),
(x"5555_4444", BEn_0000, PAR_OK, CONT_DATA),
(x"3333_2222", BEn_0000, PAR_OK, CONT_DATA),
(x"1111_0000", BEn_0000, PAR_OK, LAST_DATA ) );
pci_memory_burst_write (x"b000_0018", PAR_OK, xsva_set_data,
clk, trdy_n, devsel_n, frame_n, ad, c_be_n, irdy_n, par);
----------------------------------
-- 0x000_001x memory burst read
pci_memory_burst_read (x"b000_0018", PAR_OK, DATA_No_4, (BEn_0000, BEn_0000, BEn_0000, BEn_0000),
clk, trdy_n, devsel_n, frame_n, ad, c_be_n, irdy_n, par, perr_n, sva_read_data1);
wait until clk'event and clk = '1';
wait until clk'event and clk = '1';
wait until clk'event and clk = '1';
wait until clk'event and clk = '1';
wait;
end process;
end pci_model_sim_arch;
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